The present invention relates to a manufacturing method of a semiconductor device and, in particular, relates to a doping method of an impurity atom to a semiconductor substrate.
FIGS. 3A and 3B show a conventional shallow doping process for a planer semiconductor substrate 1 so as to have a junction depth of around 20 nm.
By irradiating a low energy ion beam 4, ton implantation is usually performed to the surface of the semiconductor substrate 1 at a perpendicular implantation angle or a nearly perpendicular implantation angle (FIG. 3A). For example, in case where the ion implantation is carried out by implantation energy of 200 eV, because the beam current value in the ion implantation is low, the ion implantation for an impurity diffused layer 5 needs a long implantation processing time to get a predetermined implantation dose amount (FIG. 3B).
Referring to FIGS. 4A to 4C, by using a silicon substrate 1a as a semiconductor substrate, a thin film 3 is formed on the silicon substrate 1a surface with a plasma 2 including the impurity atom [chemical vapor deposition (CVD) method or physical vapor deposition (PVD) method] (FIGS. 4A and 4B). Thereafter, an impurity diffused layer 5 is formed by thermally diffusing the impurity atom such as B (Boron) from the thin film 3 within the silicon substrate is with a heat treatment (FIG. 4C).
In this case, because there is a natural oxide film on the surface of the substrate, the surface of the substrate does not become the high impurity concentration. Therefore it is hard to carry out a thermal diffusion to enough concentration as source/drain.
FIG. 5 shows a conventional technique about a case that the ion implantation is carded out to the side (a wall and a slope part) of a concavity and convexity part of the semiconductor substrate formed by processing. Here, the concavity and convexity part represents a space structure having a projection, a ditch, a step, a slope, and the like.
In a process 1, a semiconductor substrate 1 for Fin-FET type transistors having the projection is made by selectivity performing etching by the use of a mask 6. In a process 2, the ion is implanted into the projection with irradiating an ion beam 4 including impurity atoms B from a diagonal course. Thereafter the heat-treatment is carried out. As a result, a diffused layer 5 of the impurity atom is formed to a sidewall of the projection.
In case where the ion implantation angle (Tilt angle) from a perpendicular line is small, e.g., in the case of 10 degrees, it is necessary to process it with an implantation dose amount of 6 times in comparison with the case for the plane. Therefore, a very long implantation processing time is necessary regardless of an advantageous condition that a beam current density level is low. This is lack in practical utility.
Besides, by a reflection of the implantation ion in the substrate surface, a loss of the implantation ion is occurred, and therefore more dose amount is needed.
As mentioned above, in the above conventional method, the ion implantation of low energy is necessary to form a shallow impurity diffused layer Into the silicon substrate. And, in the ion implantation of the low energy, it is impossible to obtain a high beam current density because of an ion beam divergence phenomenon caused by a space-charge effect. Therefore, in the low energy ion implantation of the dose amount which is near to 1E15atoms/cm2, a very long implantation processing time is required for the ion implantation. Further, a great cost up in manufacturing was caused.
As another disadvantage, like a Fin-FET type transistor of the three-dimensional structure that becomes the topic in recent years, the shallow ion implantation is necessary for a wall of the nearly perpendicular projection that was formed three-dimensionally to the silicon substrate.
The Fin-FET type transistor will be described with reference to FIG. 10. On the semiconductor substrate 1, a projection (extension) which becomes a drain D, a channel, and a source S is formed by etching process or the like. A part which becomes a gate G is formed so as to cover over the channel between the source and the drain.
In the shallow ion implantation for the wall of the nearly perpendicular projection of the Fin-FET type transistor having the three-dimensional structure, when an ion implantation is performed directly, the implantation angle θ is a high angle to the wall of the projection. Therefore, the ions are implanted into the silicon substrate with only the dose amount defined by sinθ. Therefore the ion implantation of higher dose amount was necessary, and a problem has occurred in practical utility.
In addition, as shown in FIGS. 4A to 4C, there is a method for diffusing an impurity atom within the silicon substrate 1a by a thermal diffusion processing after the thin film 3 including the impurity atom has formed with the plasma 2. In this method, it is difficult to carry out the thermal diffusion more than 1E18cm-3 in the recent process that high temperature heat-treatment is impossible. For the reason, there was not useful means that can realize a Fin-FET type transistor.
Furthermore, with the miniaturization of the LSI device, the implantation of the impurity atom to the region which is called the extension of the source/drain region becomes more shallow. However, the amount of the implanted impurity atom remains with an approximately constant value. On the other hand, in a conventional ion implantation technology, the energy of the ion beam falls down as the implantation depth becomes shallow. Therefore the beam current deteriorates under the influence of the space-charge effect, and the productivity also deteriorates.
In order to avoid this problem, a existing plan for reduction or restraint of the following substantial space-charge effect is proposed, and is put to practical use.
(1) The technique that uses the electron in the conventional beam transport system.
(2) The technique that transports the ion beam with high energy and decelerates it just before a wafer.
(3) Technique that ionizes polyatomic molecule and transports it.
In addition, in substitution for a conventional beam line type ion implantation,
(4) the technique which is called a plasma doping is examined. However, none of the above-mentioned techniques is yet fixed as the technique to improve the productivity crucially.
The further miniaturization (or shrink) of the LSI device promotes the shape change of the transistor, and a space structure which is so-called 3D is being adopted. In this case, as for the ion implantation to source/drain, the doping to the surface that is perpendicular to the plane of the semiconductor substrate is required. In this event, the ion implantation of the small angle with a normal line of a perpendicular surface is impossible because the distance between adjacent transistors cannot be secured enough. For the reason, two following problems are caused from the viewpoint of the productivity. Then the problem that the productivity decreases far than a case of a planar transistor happens.
The first problem is a simple geometric problem. Only the implantation particles of the number defined by the angle that sinθ was multiplied by the implantation angle θ arrive at a perpendicular surface of the transistor having the space structure. Generally, the efficiency of the implantation becomes equal or less than 34% because the implantation angle θ is equal or less than 20 degrees. That is the productivity of this process becomes equal or lower than one third.
As for another problem, in the ion implantation of the low-energy/low-implantation angle, the ion is reflected at the substrate surface and is hard to implant into the substrate. Therefore the degradation of the productivity occurs. At the implantation angle equal or less than 20 degrees, only the ions of 67% are implanted, therefore the productivity becomes two-thirds.
If the above two problems are joined, in the low angle implantation to the perpendicular surface, only the productivity of 2/9, namely, equal or less than 22%, can be achieved in comparison with the implantation to the plane. Accordingly, the low productivity that becomes the problem in the current planer transistor will turn worse more than around 5 times or more,